1. Field of the Invention
The invention relates to the field of semiconductor memory arrays, and in particular to reducing the semiconductor area of a wordline decoder.
2. Description of the Related Art
Two classes of local wordline decoders each utilizing three transistors are known in the related art. The circuits for these local wordline decoders are shown in FIGS. 1a and 1b. A circuit 100 for decoding a line 0 and an identical circuit 110 for decoding a line 1 are shown. P-channel transistor 101 (P1) and n-channel transistor 102 (N1) are connected in series between wordline driver input 107 and a reference potential 109. Input 104 (mwln0) connects to the gate of transistor 101 and 102. Output 106 (lwl0) is connected to the junction of transistors 101 and 102. Drain and source of n-channel transistor 103 (N11) are connected between output 106 and reference potential 109. The gate of transistor 103 is connected to input 108 (wldrn), which is the inverse of input 107.
Referring now to FIG. 1b, circuit 110 is explained next. P-channel transistor 111 (P2) and n-channel transistor 112 (N2) are connected in series between wordline driver input 107 and a reference potential 109. Input 114 (mwln1) connects to the gate of transistor 111 and 112. Output 116 (lwl1) is connected to the junction of transistors 111 and 112. Drain and source of n-channel transistor 113 (N21) are connected between output 116 and reference potential 109. The gate of transistor 113 is connected to input 108 (wldrn), which is the inverse of input 107.
Referring now to FIG. 2, we show a physical layout for the circuit of FIGS. 1a/1b. Transistors 101 (P1), 102 (N1), 103 (N11), 111 (P2), 112 (N2), and 113 (N21) are shown in an orthogonal arrangement of three columns and two rows. Dimension y is determined by the memory cell pitch. Referring now to FIG. 3, we show a more detailed layout of transistors N1, and N2. 401 and 402 are the active areas (AA) or n-type regions (source and drain) of transistor N1. Region 405 is the metal oxide gate of N1. 403 and 404 are the AA or n-type regions (source and drain) of transistor N2. Region 406 is the metal oxide gate of N2. N-type regions 402 and 403 connect to outputs 106 (lwl0) and 116 (lwl1) respectively.
U.S. Pat. No. 5,446,698 (McClure) discloses a redundant global wordline for local wordlines, however, the details of the local wordline decoder are not discussed. U.S. Pat. No. 5,587,960 (Ferris) describes a semiconductor memory with sub-wordlines but does not describe the details of the sub-wordline decoder.